1. Field of the Invention
The present invention relates to a carrier regenerating circuit having an automatic frequency controlling function which is used for multi-level quadrature amplitude demodulation.
2. Description of the Related Art
FIG. 6 shows the prior art reference 1. This is a carrier regenerating circuit having an frequency synchronizing function. The circuit shown in FIG. 6 is disclosed in Japanese Patent Application Laid-Open No. Hei-5-91154. The carrier regenerating circuit comprises quadrature phase detecting circuit 31, first multi-level discriminating circuit 32, phase error detecting circuit 33, first LPF (low pass filter) 34, VCO (voltage controlled oscillator) 35, second multi-level discriminating circuit 36, correlation calculating circuit 37, decision circuit 38, switch 39, second LPF 40, and synthesizing circuit 41.
Quadrature phase detecting circuit 31 is supplied with quadrature phase modulated signal `a` from an input terminal and regenerated carrier `e` supplied by VCO 35. Quadrature phase detecting circuit 31 generates baseband signal `b` by synchronous detection of quadrature phase modulated signal `a` using regenerated carrier `e`. Two baseband signals `b` are supplied to first multi-level discriminating circuit 32 and second multi-level discriminating circuit 36. The discriminating time of the first multi-level discriminating circuit 32 is set to discriminate the aperture of an eye pattern and the discriminating time of the second multi-level discriminating circuit 36 is set to discriminate the middle point between adjoining apertures. First discriminating circuit 32 outputs main demodulated signals DI, DQ and error signals EI, EQ. The outputs of discriminating circuit 32 are supplied to phase error detecting circuit 33, correlation calculating circuit 37, and decision circuit 38. Phase error detecting circuit 33 logically processes input signals to generate phase error signal `c` which is used to control the oscillating phase of VCO 35. LPF 34 eliminates unnecessary components of phase error signal `c` to generate main controlling signal `d`.
Second multi-level discriminating circuit 36 discriminates the level of sampled signals and supplies the result of the discrimination to correlation calculating circuit 37 and decision circuit 38. Correlation calculating circuit 37 calculates the correlation between the outputs of first multi-level discriminating circuit 32 and the outputs of second multi-level discriminating circuit to generate a controlling signal for AFC (automatic frequency control) `f`. Decision circuit 38 determines whether the two demodulated main signals of quadrature phase detecting circuit 31 simultaneously change and whether the level of the output of second multi-level discriminating circuit 36 exceeds a predetermined threshold based on the outputs of first multi-level discriminating circuit 32 and of second multi-level discriminating circuit 36, thereby outputting control signal `g` for controlling switch 39. Switch 39 is closed when control signal `g` is active. LPF 40 eliminates unnecessary components of controlling signal for AFC `h`. The output of LPF 40 is added to main controlling signal `d` in synthesizing circuit 41. The synthesized output signal of synthesizing circuit 41 is applied to VCO 35 where regenerated carrier `e` is controlled by the synthesized output signal.
As the prior art reference 2, Japanese Patent Application Laid-Open No. Hei-7-250118 discloses a carrier regenerating circuit which is used by a demodulator in a digital signal transmission system adapting phase modulation such as BPSK (Binary Phase Shift Keying) and QPSK (Quadrature Phase Shift Keying). This carrier regenerating circuit features the wide carrier capture range and small scale. This carrier regenerating circuit forms a feedback loop which comprises a functional unit, a phase detecting circuit, a loop filter, a VCO and a ROM table. In this carrier regenerating circuit, the phase error output of the phase detecting circuit is processed in a square multiplier and LPF and then fed to a comparator. When this carrier regenerating circuit fall into pseudo synchronization, outputs of a delay circuit in the loop filter, of a delay circuit in the VCO, and of a delay circuit in the LPF are set to zero by the output of comparator. The loop filter comprises a limiter and outputs zero when input level exceeds limit level while it is in the second pseudo synchronizing state to proceed to the reset state.
As the prior art reference 3, Japanese Patent Application Laid-Open No. Hei-5-83320 discloses a carrier synchronizing circuit. This carrier synchronizing circuit is digitized and switches signal point to get phase information in the process of synchronization, thereby resulting in wide synchronizing capture range and short capture time. In this carrier synchronizing circuit, the phase error signal for controlling VCO, which regenerates carrier, is derived by manipulating logically the specific signal and error signal. The specific signal is one of demodulated signals which is generated from 16-value quadrature amplitude modulated signal. A logic circuit outputs a signal-point-detecting signal of negative logic only when 16-value quadrature amplitude modulated signal is at a specific signal point. The VCO outputs a carrier synchronization detecting signal of negative logic. In this carrier synchronizing circuit, the signal-point-detecting signal, the carrier synchronization detecting signal, and regenerated clock are logically manipulated and synchronized with a clock signal in a flip-flop so as to feedback the phase error signal only at specific a signal point to VCO before carrier synchronization has established. In the process of establishing carrier synchronization, error rate is monitored in a error rate finding circuit and the specific signal point, which the logic circuit detect, is altered to all signal points when error rate becomes less than predetermined value.
The prior art reference 1 has the disadvantages as follows.
The gain of frequency deviation detection decreases when the carrier regenerating circuit is applied to multi-level QAM (quadrature amplitude modulation) signal because it is designed for QPSK signal. Although the carrier regenerating circuit necessitates the signal locus which runs along a diagonal line on phase plane, such signal locus rarely arises in multi-level QAM signal because there are many signal points in multi-level QAM signal. Thus, it is difficult to apply the carrier regenerating circuit to multi-level QAM.
Further there is the disadvantage that the frequency judgement cannot be made before the phase synchronization has established. This is because the change of signal point from one to another along a diagonal line on phase plane cannot be detected if signal points are not in the proper position.
The prior art reference 2 also has similar disadvantages to the prior art reference 1 because it is designed for demodulating BPSK signal or QPSK signal.
Although the prior art reference 3 relates to the carrier synchronizing circuit for multi-level QAM signal, it has no AFC function and is different in structure from the present invention.